An FPGA-based hardware-efficient fault-tolerant astrocyte-neuron network

A. P. Johnson, D. M. Halliday, A. M. Tyrrell, A. G. Millard, J. Timmis, Junxiu Liu, Jim Harkin, Liam McDaid, S. Karim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

The human brain is structured with the capacity to repair itself. This plasticity of the brain has motivated researchers to develop systems which have similar capabilities of fault tolerance and self-repair. Recent research findings have proven that interactions between astrocytes and neurons can actuate brain-like self-repair in a bidirectionally coupled astrocyte-neuron system. This paper presents a hardware realization of the bio-inspired self-repair architecture on an FPGA. We also introduce a reduced architecture for an FPGA-based hardware-efficient fault-tolerant system. This is based on the principle of retrograde signaling in an astrocyte-neuron network by simplifying the calcium dynamics within the astrocyte. The hardware optimized implementation shows more than a 90 decrease in hardware utilization and proves an efficient implementation for a large-scale astrocyte-neuron network. An Average spike rate of 0:027 spikes per clock cycle were observed for both the proposed models of astrocytes in the case of 100 partial fault.
LanguageEnglish
Title of host publicationUnknown Host Publication
Pages1-8
Number of pages8
DOIs
Publication statusAccepted/In press - 26 Sep 2016
Event2016 IEEE Symposium Series on Computational Intelligence (SSCI) -
Duration: 26 Sep 2016 → …

Conference

Conference2016 IEEE Symposium Series on Computational Intelligence (SSCI)
Period26/09/16 → …

Fingerprint

Neurons
Field programmable gate arrays (FPGA)
Hardware
Repair
Brain
Fault tolerance
Plasticity
Astrocytes
Clocks
Calcium

Keywords

  • biology computing
  • biomimetics
  • brain
  • fault tolerance
  • field programmable gate arrays
  • neurophysiology
  • FPGA-based hardware-efficient fault-tolerant astrocyte-neuron network
  • astrocyte calcium dynamics
  • bidirectionally coupled astrocyte-neuron system
  • bio-inspired self-repair architecture
  • brain plasticity
  • brain-like self-repair actuation
  • hardware optimized implementation
  • hardware realization
  • human brain
  • large-scale astrocyte-neuron network
  • retrograde signaling
  • Biological system modeling
  • Calcium
  • Fault tolerance
  • Fault tolerant systems
  • Hardware
  • Mathematical model
  • Neurons

Cite this

Johnson, A. P., Halliday, D. M., Tyrrell, A. M., Millard, A. G., Timmis, J., Liu, J., ... Karim, S. (Accepted/In press). An FPGA-based hardware-efficient fault-tolerant astrocyte-neuron network. In Unknown Host Publication (pp. 1-8) https://doi.org/10.1109/SSCI.2016.7850175
Johnson, A. P. ; Halliday, D. M. ; Tyrrell, A. M. ; Millard, A. G. ; Timmis, J. ; Liu, Junxiu ; Harkin, Jim ; McDaid, Liam ; Karim, S. / An FPGA-based hardware-efficient fault-tolerant astrocyte-neuron network. Unknown Host Publication. 2016. pp. 1-8
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Johnson, AP, Halliday, DM, Tyrrell, AM, Millard, AG, Timmis, J, Liu, J, Harkin, J, McDaid, L & Karim, S 2016, An FPGA-based hardware-efficient fault-tolerant astrocyte-neuron network. in Unknown Host Publication. pp. 1-8, 2016 IEEE Symposium Series on Computational Intelligence (SSCI), 26/09/16. https://doi.org/10.1109/SSCI.2016.7850175

An FPGA-based hardware-efficient fault-tolerant astrocyte-neuron network. / Johnson, A. P.; Halliday, D. M.; Tyrrell, A. M.; Millard, A. G.; Timmis, J.; Liu, Junxiu; Harkin, Jim; McDaid, Liam; Karim, S.

Unknown Host Publication. 2016. p. 1-8.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Johnson AP, Halliday DM, Tyrrell AM, Millard AG, Timmis J, Liu J et al. An FPGA-based hardware-efficient fault-tolerant astrocyte-neuron network. In Unknown Host Publication. 2016. p. 1-8 https://doi.org/10.1109/SSCI.2016.7850175