An Energy-Efficient Artefact Detection Accelerator on FPGAs for Hyper-Spectral Satellite Imagery

Cornell Castelino, Shashwat Khandelwal, Shanker Shreejith, Sharatchandra Varma Bogaraju

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

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Abstract

Hyper-Spectral Imaging (HSI) is a crucial technique used to analyse remote sensing data acquired from Earth observation satellites. The rich spatial and spectral information obtained through HSI allows for better characterisation and exploration of the Earth's surface over traditional techniques like RGB and Multi-Spectral imaging on the downlinked image data at ground stations. In some cases, these images do not contain meaningful information due to the presence of clouds or other artefacts, limiting their usefulness. Transmission of such artefact HSI images leads to wasteful use of already scarce energy and time costs required for communication. While detecting such artefacts prior to transmitting the HSI image is desirable, the computational complexity of these algorithms and the limited power budget on satellites (especially CubeSats) are key constraints. This paper presents an unsupervised learning-based convolutional autoencoder (CAE) model for artefact identification of acquired HSI images at the satellite and a deployment architecture on AMD's Zynq Ultrascale FPGAs. The model is trained and tested on widely used HSI image datasets: Indian Pines, Salinas Valley, the University of Pavia and the Kennedy Space Center. For deployment, the model is quantised to 8-bit precision, fine-tuned using the Vitis-AI framework and integrated as a subordinate accelerator using AMD's Deep-Learning Processing Units (DPU) instance on the Zynq device. Our tests show that the model can process each spectral band in an HSI image in 4 ms, 2.6× better than INT8 inference on Nvidia's Jetson platform & 1.27× better than SOTA artefact detectors. Our model also achieves an fl-score of 92.8 % and FPR of 0 % across the dataset, while consuming 21.52 mJ per HSI image, 3.6 ×better than INT8 Jetson inference & 7.5 × better than SOTA artefact detectors, making it a viable architecture for deployment in CubeSats.
Original languageEnglish
Title of host publicationProceedings - 2024 27th Euromicro Conference on Digital System Design, DSD 2024
EditorsTomasz Kryjak, Frederic Petrot
PublisherIEEE
Pages551-558
Number of pages8
ISBN (Electronic)979-8-3503-8038-5
ISBN (Print)979-8-3503-8039-2
DOIs
Publication statusPublished online - 6 Nov 2024
Event27th Euromicro Conference on Digital System Design - Paris, France
Duration: 28 Aug 202430 Aug 2024

Publication series

Name
PublisherIEEE Control Society
ISSN (Print)2639-3859
ISSN (Electronic)2771-2508

Conference

Conference27th Euromicro Conference on Digital System Design
Country/TerritoryFrance
CityParis
Period28/08/2430/08/24

Bibliographical note

Publisher Copyright:
© 2024 IEEE.

Keywords

  • Analytical models
  • Satellites
  • computational modeling
  • Detectors
  • Computer architecture
  • Energy efficiency
  • Satellite images
  • IP networks
  • CubeSat
  • field programmable gate arrays

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