An Efficient, Low-Cost Routing Architecture for Spiking Neural Network Hardware Implementations

Yuling Luo, Lei Wan, Junxiu Liu, Jim Harkin, Yi Cao

Research output: Contribution to journalArticle

4 Citations (Scopus)

Abstract

The basic processing units in brain are neurons and synapses that are interconnected in a complex pattern and show many surprised information processing capabilities. The researchers attempt to mimic this efficiency and build artificial neural systems in hardware device to emulate the key information processing principles of the brain. However, the neural network hardware system has a challenge of interconnecting neurons and synapses efficiently. An efficient, low-cost routing architecture (ELRA) is proposed in this paper to provide a communication infrastructure for the hardware spiking neuron networks (SNN). A dynamic traffic arbitration strategy is employed in ELRA, where the traffic status weights of input ports are calculated in real-time according to the channel traffic statuses and the port with the largest traffic status weight is given a high priority to forward packets. This strategy enables the router to serve congested ports preferentially, which can balance the overall network traffic loads. Experimental results show the feasibility of ELRA under various traffic scenarios, and the hardware synthesis result using SAED 90 nm technology demonstrates it has a low hardware area overhead which maintains scalability for large-scale SNN hardware implementations.
Original languageEnglish
Pages (from-to)1777-1788
JournalNeural Processing Letters
Volume48
Issue number3
Early online date9 Feb 2018
DOIs
Publication statusPublished - Dec 2018

Keywords

  • Neural network
  • Networks-on-chip
  • hardware
  • FPGA
  • scalability
  • interconnect

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