An efficient FPGA-based dynamic partial reconfiguration design flow and environment for image and signal processing IP cores

B Krill, A Ahmad, A Amira, H Rabah

    Research output: Contribution to journalArticle

    24 Citations (Scopus)
    LanguageEnglish
    Pages377
    JournalSignal Processing: Image Communication
    Volume25
    Issue number5
    DOIs
    Publication statusPublished - 2010

    Cite this

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    title = "An efficient FPGA-based dynamic partial reconfiguration design flow and environment for image and signal processing IP cores",
    author = "B Krill and A Ahmad and A Amira and H Rabah",
    year = "2010",
    doi = "10.1016/j.image.2010.04.005",
    language = "English",
    volume = "25",
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    An efficient FPGA-based dynamic partial reconfiguration design flow and environment for image and signal processing IP cores. / Krill, B; Ahmad, A; Amira, A; Rabah, H.

    Vol. 25, No. 5, 2010, p. 377.

    Research output: Contribution to journalArticle

    TY - JOUR

    T1 - An efficient FPGA-based dynamic partial reconfiguration design flow and environment for image and signal processing IP cores

    AU - Krill, B

    AU - Ahmad, A

    AU - Amira, A

    AU - Rabah, H

    PY - 2010

    Y1 - 2010

    U2 - 10.1016/j.image.2010.04.005

    DO - 10.1016/j.image.2010.04.005

    M3 - Article

    VL - 25

    SP - 377

    IS - 5

    ER -