Abstract
Colour space conversion is very important in many types of image processing applications including video compression. This operation consumes up to 40% of the entire processing power of a highly optimised decoder. Therefore, techniques which efficiently implement this conversion are desired. This paper presents two novel architectures for efficient implementation of a Colour Space Converter (CSC) suitable for Field Programmable Gate Array (FPGAs) and VLSI. The proposed architectures are based on Distributed Arithmetic (DA) ROM accumulator principles. The architectures have been implemented and verified using the Celoxica RC1000 FPGA development board. In addition, they are platform independent and have a low latency (eight cycles). The first architecture has a throughput of height, while the second one is fully pipelined and has a throughput of one and capable of sustained data rate of over 234 mega-conversions/s. (c) 2005 Elsevier B.V. All rights reserved.
| Original language | English |
|---|---|
| Pages (from-to) | 935-942 |
| Journal | Image and Vision Computing |
| Volume | 23 |
| Issue number | 11 |
| DOIs | |
| Publication status | Published - Oct 2005 |
Keywords
- colour space conversion
- field programmable gate array
- distributed arithmetic
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Cite this
Bensaali, F., & Amira, A. (2005). Accelerating colour space conversion on reconfigurable hardware. Image and Vision Computing, 23(11), 935-942. https://doi.org/10.1016/j.imavis.2005.03.006