Accelerating colour space conversion on reconfigurable hardware

F Bensaali, A Amira

    Research output: Contribution to journalArticle

    18 Citations (Scopus)

    Abstract

    Colour space conversion is very important in many types of image processing applications including video compression. This operation consumes up to 40% of the entire processing power of a highly optimised decoder. Therefore, techniques which efficiently implement this conversion are desired. This paper presents two novel architectures for efficient implementation of a Colour Space Converter (CSC) suitable for Field Programmable Gate Array (FPGAs) and VLSI. The proposed architectures are based on Distributed Arithmetic (DA) ROM accumulator principles. The architectures have been implemented and verified using the Celoxica RC1000 FPGA development board. In addition, they are platform independent and have a low latency (eight cycles). The first architecture has a throughput of height, while the second one is fully pipelined and has a throughput of one and capable of sustained data rate of over 234 mega-conversions/s. (c) 2005 Elsevier B.V. All rights reserved.
    LanguageEnglish
    Pages935-942
    JournalImage and Vision Computing
    Volume23
    Issue number11
    DOIs
    Publication statusPublished - Oct 2005

    Fingerprint

    Reconfigurable hardware
    Field programmable gate arrays (FPGA)
    Throughput
    Color
    ROM
    Image compression
    Image processing
    Processing

    Keywords

    • colour space conversion
    • field programmable gate array
    • distributed arithmetic

    Cite this

    Bensaali, F ; Amira, A. / Accelerating colour space conversion on reconfigurable hardware. In: Image and Vision Computing. 2005 ; Vol. 23, No. 11. pp. 935-942.
    @article{9fb8216125ee4a61adb6dcce2f0911a0,
    title = "Accelerating colour space conversion on reconfigurable hardware",
    abstract = "Colour space conversion is very important in many types of image processing applications including video compression. This operation consumes up to 40{\%} of the entire processing power of a highly optimised decoder. Therefore, techniques which efficiently implement this conversion are desired. This paper presents two novel architectures for efficient implementation of a Colour Space Converter (CSC) suitable for Field Programmable Gate Array (FPGAs) and VLSI. The proposed architectures are based on Distributed Arithmetic (DA) ROM accumulator principles. The architectures have been implemented and verified using the Celoxica RC1000 FPGA development board. In addition, they are platform independent and have a low latency (eight cycles). The first architecture has a throughput of height, while the second one is fully pipelined and has a throughput of one and capable of sustained data rate of over 234 mega-conversions/s. (c) 2005 Elsevier B.V. All rights reserved.",
    keywords = "colour space conversion, field programmable gate array, distributed arithmetic",
    author = "F Bensaali and A Amira",
    year = "2005",
    month = "10",
    doi = "10.1016/j.imavis.2005.03.006",
    language = "English",
    volume = "23",
    pages = "935--942",
    journal = "Image and Vision Computing",
    issn = "0262-8856",
    publisher = "Elsevier",
    number = "11",

    }

    Accelerating colour space conversion on reconfigurable hardware. / Bensaali, F; Amira, A.

    In: Image and Vision Computing, Vol. 23, No. 11, 10.2005, p. 935-942.

    Research output: Contribution to journalArticle

    TY - JOUR

    T1 - Accelerating colour space conversion on reconfigurable hardware

    AU - Bensaali, F

    AU - Amira, A

    PY - 2005/10

    Y1 - 2005/10

    N2 - Colour space conversion is very important in many types of image processing applications including video compression. This operation consumes up to 40% of the entire processing power of a highly optimised decoder. Therefore, techniques which efficiently implement this conversion are desired. This paper presents two novel architectures for efficient implementation of a Colour Space Converter (CSC) suitable for Field Programmable Gate Array (FPGAs) and VLSI. The proposed architectures are based on Distributed Arithmetic (DA) ROM accumulator principles. The architectures have been implemented and verified using the Celoxica RC1000 FPGA development board. In addition, they are platform independent and have a low latency (eight cycles). The first architecture has a throughput of height, while the second one is fully pipelined and has a throughput of one and capable of sustained data rate of over 234 mega-conversions/s. (c) 2005 Elsevier B.V. All rights reserved.

    AB - Colour space conversion is very important in many types of image processing applications including video compression. This operation consumes up to 40% of the entire processing power of a highly optimised decoder. Therefore, techniques which efficiently implement this conversion are desired. This paper presents two novel architectures for efficient implementation of a Colour Space Converter (CSC) suitable for Field Programmable Gate Array (FPGAs) and VLSI. The proposed architectures are based on Distributed Arithmetic (DA) ROM accumulator principles. The architectures have been implemented and verified using the Celoxica RC1000 FPGA development board. In addition, they are platform independent and have a low latency (eight cycles). The first architecture has a throughput of height, while the second one is fully pipelined and has a throughput of one and capable of sustained data rate of over 234 mega-conversions/s. (c) 2005 Elsevier B.V. All rights reserved.

    KW - colour space conversion

    KW - field programmable gate array

    KW - distributed arithmetic

    U2 - 10.1016/j.imavis.2005.03.006

    DO - 10.1016/j.imavis.2005.03.006

    M3 - Article

    VL - 23

    SP - 935

    EP - 942

    JO - Image and Vision Computing

    T2 - Image and Vision Computing

    JF - Image and Vision Computing

    SN - 0262-8856

    IS - 11

    ER -