Accelerating colour space conversion on reconfigurable hardware

F Bensaali; A Amira

doi:10.1016/j.imavis.2005.03.006

Accelerating colour space conversion on reconfigurable hardware

F Bensaali, A Amira

Research output: Contribution to journal › Article › peer-review

18 Citations (Scopus)

Abstract

Colour space conversion is very important in many types of image processing applications including video compression. This operation consumes up to 40% of the entire processing power of a highly optimised decoder. Therefore, techniques which efficiently implement this conversion are desired. This paper presents two novel architectures for efficient implementation of a Colour Space Converter (CSC) suitable for Field Programmable Gate Array (FPGAs) and VLSI. The proposed architectures are based on Distributed Arithmetic (DA) ROM accumulator principles. The architectures have been implemented and verified using the Celoxica RC1000 FPGA development board. In addition, they are platform independent and have a low latency (eight cycles). The first architecture has a throughput of height, while the second one is fully pipelined and has a throughput of one and capable of sustained data rate of over 234 mega-conversions/s. (c) 2005 Elsevier B.V. All rights reserved.

Original language	English
Pages (from-to)	935-942
Journal	Image and Vision Computing
Volume	23
Issue number	11
DOIs	https://doi.org/10.1016/j.imavis.2005.03.006
Publication status	Published - Oct 2005

Keywords

colour space conversion
field programmable gate array
distributed arithmetic

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10.1016/j.imavis.2005.03.006

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abstract = "Colour space conversion is very important in many types of image processing applications including video compression. This operation consumes up to 40% of the entire processing power of a highly optimised decoder. Therefore, techniques which efficiently implement this conversion are desired. This paper presents two novel architectures for efficient implementation of a Colour Space Converter (CSC) suitable for Field Programmable Gate Array (FPGAs) and VLSI. The proposed architectures are based on Distributed Arithmetic (DA) ROM accumulator principles. The architectures have been implemented and verified using the Celoxica RC1000 FPGA development board. In addition, they are platform independent and have a low latency (eight cycles). The first architecture has a throughput of height, while the second one is fully pipelined and has a throughput of one and capable of sustained data rate of over 234 mega-conversions/s. (c) 2005 Elsevier B.V. All rights reserved.",

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AU - Amira, A

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AB - Colour space conversion is very important in many types of image processing applications including video compression. This operation consumes up to 40% of the entire processing power of a highly optimised decoder. Therefore, techniques which efficiently implement this conversion are desired. This paper presents two novel architectures for efficient implementation of a Colour Space Converter (CSC) suitable for Field Programmable Gate Array (FPGAs) and VLSI. The proposed architectures are based on Distributed Arithmetic (DA) ROM accumulator principles. The architectures have been implemented and verified using the Celoxica RC1000 FPGA development board. In addition, they are platform independent and have a low latency (eight cycles). The first architecture has a throughput of height, while the second one is fully pipelined and has a throughput of one and capable of sustained data rate of over 234 mega-conversions/s. (c) 2005 Elsevier B.V. All rights reserved.

KW - colour space conversion

KW - field programmable gate array

KW - distributed arithmetic

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DO - 10.1016/j.imavis.2005.03.006

M3 - Article

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EP - 942

JO - Image and Vision Computing

JF - Image and Vision Computing

SN - 0262-8856

IS - 11

ER -

Accelerating colour space conversion on reconfigurable hardware

Abstract

Keywords

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