This paper presents a hardware implementation of a Time Multiplexing Architecture (TMA) that can interconnect arrays of neurons in an Artificial Neural Network (ANN) using a single metal wire. The approach exploits the relative slow operational speed of the biological system by using fast digital hardware to sequentially sample neurons in a layer and transmit the associated spikes to neurons in other layers. The motivation for this work is to develop minimal area inter-neuron communication hardware. An estimate of the density of on-chip neurons afforded by this approach is presented. The paper verifies the operation of the TMA and investigates pulse transmission errors as a function of the sampling rate. Simulations using the Xilinx System Generator (XSG) package demonstrate that the effect of these errors on the performance of an SNN, pre-trained to solve the XOR problem, is negligible if the sampling frequency is sufficiently high.
|Title of host publication||Unknown Host Publication|
|Number of pages||8|
|Publication status||Published - 2006|
|Event||16th International Conference on Artificial Neural Networks - ICANN 2006 - Athens, Greece|
Duration: 1 Jan 2006 → …
|Conference||16th International Conference on Artificial Neural Networks - ICANN 2006|
|Period||1/01/06 → …|