A Time Multiplexing Architecture for Inter-neuron Communications

Fergal Tuffy, Liam McDaid, Martin McGinnity, Jose Santos, Peter Kelly, Vunfu Wong Kwan, John Alderman

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper presents a hardware implementation of a Time Multiplexing Architecture (TMA) that can interconnect arrays of neurons in an Artificial Neural Network (ANN) using a single metal wire. The approach exploits the relative slow operational speed of the biological system by using fast digital hardware to sequentially sample neurons in a layer and transmit the associated spikes to neurons in other layers. The motivation for this work is to develop minimal area inter-neuron communication hardware. An estimate of the density of on-chip neurons afforded by this approach is presented. The paper verifies the operation of the TMA and investigates pulse transmission errors as a function of the sampling rate. Simulations using the Xilinx System Generator (XSG) package demonstrate that the effect of these errors on the performance of an SNN, pre-trained to solve the XOR problem, is negligible if the sampling frequency is sufficiently high.
LanguageEnglish
Title of host publicationUnknown Host Publication
Pages944-952
Number of pages8
Volume4131
DOIs
Publication statusPublished - 2006
Event16th International Conference on Artificial Neural Networks - ICANN 2006 - Athens, Greece
Duration: 1 Jan 2006 → …

Conference

Conference16th International Conference on Artificial Neural Networks - ICANN 2006
Period1/01/06 → …

Fingerprint

Multiplexing
Neurons
Communication
Hardware
Sampling
Biological systems
Wire
Neural networks
Metals

Cite this

Tuffy, F., McDaid, L., McGinnity, M., Santos, J., Kelly, P., Kwan, V. W., & Alderman, J. (2006). A Time Multiplexing Architecture for Inter-neuron Communications. In Unknown Host Publication (Vol. 4131, pp. 944-952) https://doi.org/10.1007/11840817_98
Tuffy, Fergal ; McDaid, Liam ; McGinnity, Martin ; Santos, Jose ; Kelly, Peter ; Kwan, Vunfu Wong ; Alderman, John. / A Time Multiplexing Architecture for Inter-neuron Communications. Unknown Host Publication. Vol. 4131 2006. pp. 944-952
@inproceedings{3dfd5151191b41159c7291b0cd8c2354,
title = "A Time Multiplexing Architecture for Inter-neuron Communications",
abstract = "This paper presents a hardware implementation of a Time Multiplexing Architecture (TMA) that can interconnect arrays of neurons in an Artificial Neural Network (ANN) using a single metal wire. The approach exploits the relative slow operational speed of the biological system by using fast digital hardware to sequentially sample neurons in a layer and transmit the associated spikes to neurons in other layers. The motivation for this work is to develop minimal area inter-neuron communication hardware. An estimate of the density of on-chip neurons afforded by this approach is presented. The paper verifies the operation of the TMA and investigates pulse transmission errors as a function of the sampling rate. Simulations using the Xilinx System Generator (XSG) package demonstrate that the effect of these errors on the performance of an SNN, pre-trained to solve the XOR problem, is negligible if the sampling frequency is sufficiently high.",
author = "Fergal Tuffy and Liam McDaid and Martin McGinnity and Jose Santos and Peter Kelly and Kwan, {Vunfu Wong} and John Alderman",
note = "Reference text: 1. Roche, B., McGinnity, T.M., Maguire, L.P., McDaid, L.J.: Signalling Techniques and their Effect on Neural Network Implementation Sizes”, Information Sciences 132, pages 67-82, NH Elsevier, 2001 2. Murray, F., and Woodburn, R.: The Prospects for Analogue Neural VLSI, International Journal of Neural Systems, Vol. 8, No. 5 & 6, pages 559-579, Oct/Dec. 1997 3. Liu, S.C., Kramer, J., Indiveri, G., Delbruck, T., Burg, T., and Douglas, R.: Orientationselective VLSI Spiking Neurons, Neural Networks, Special Issue on Spiking Neurons in Neuroscience and Technology , Vol. 14, Issues 6-7, pages 629-643, July 2001 4. Diorio, C., Hsu, D., and Figueroa, M.: Adaptive CMOS: from biological inspiration to systems-on-a-chip, Proceedings of the IEEE, Vol. 90, Issue 3, pages 345 – 357, March 2002 5. Goldberg, D.H., Cauwenberghs, G., Andreou, A. G.: Probabilistic Synaptic Weighting in a Reconfigurable Network of VLSI Integrate-and-Fire Neurons, Neural Networks, Vol. 14, no. 6–7, pages 781–793, Sept 2001 6. Maass, W.: Computation with Spiking Neurons: the Handbook of Brain Theory and Neural Networks, MIT Press, 1998. 7. Noory, B., Groza, V.: A Reconfigurable Approach to Hardware Implementation of Neural Networks, IEEE CCECE 2003. Canadian Conference on Electrical and Computer Engineering, pages 1861 - 1864 Vol. 3, 4-7 May 2003 8. Chun, L., Shi, B., Chen, L.: Hardware Implementation of an Expandable On-chip Learning Neural Network with 8-Neuron and 64-Synapse, TENCON '02. Proceedings 2002 IEEE Region 10 Conference on Computers, Communications, Control and Power Engineering, Vol. 3, pages 1451 – 1454, 28-31 Oct. 2002 9. Miki, T., Editor: Brainware: Bio-Inspired Architectures and its Hardware Implementation, World Scientific Publishing Co. Ltd, 2001. 10. Johnston, S.P, Prasad, G., Maguire, L. P., McGinnity, T. M.: Comparative Investigation into Classical and Spiking Neuron Implementations on FPGAs, 15th International Conference on Artificial Neural Networks, ICANN 2005, Part 1: pages 269-274, 11-15 Sept. 2005 11. http://www.xilinx.com/ise/optional_prod/system_generator.htm 12. Tu, S.-W., Jou, J.-Y., Chang, Y.-W.: RLC Coupling-Aware Simulation for On-Chip Buses and their Encoding for Delay Reduction, 2005 ISCAS IEEE International Symposium on Circuits and Systems, 23-26 May 2005 Page(s):4134 - 4137 Vol. 4 13. Chicca, E., Badoni, D., Dante, V., D’Andreagiovanni, M., Salina, G., Carota, L., Fusi, S. and Del Giudice, P.: A VLSI Recurrent Network of Integrate and Fire Neurons Connected by Plastic Synapses with Long Term Memory”, IEEE Trans. on Neural Networks, Vol.14, No.5, Sept. 2003 14. Yamaoka, M., Osada, K., Ishibashi, K.: 0.4-V Logic-Library-Friendly SRAM Array Using Rectangular-Diffusion Cell and Delta-Boosted-Array Voltage Scheme, IEEE Journal of Solid-State Circuits, Volume 39, Issue 6, June 2004 Page(s):934 – 940 15. Naeemi, A., Meindl, J.D.: Monolayer Metallic Nanotube Interconnects: Promising Candidates or Short Local Interconnects, IEEE Electron Device Letters, Volume 26, Issue 8, Aug. 2005 Page(s):544 - 546",
year = "2006",
doi = "10.1007/11840817_98",
language = "English",
isbn = "978-3-540-38625-4",
volume = "4131",
pages = "944--952",
booktitle = "Unknown Host Publication",

}

Tuffy, F, McDaid, L, McGinnity, M, Santos, J, Kelly, P, Kwan, VW & Alderman, J 2006, A Time Multiplexing Architecture for Inter-neuron Communications. in Unknown Host Publication. vol. 4131, pp. 944-952, 16th International Conference on Artificial Neural Networks - ICANN 2006, 1/01/06. https://doi.org/10.1007/11840817_98

A Time Multiplexing Architecture for Inter-neuron Communications. / Tuffy, Fergal; McDaid, Liam; McGinnity, Martin; Santos, Jose; Kelly, Peter; Kwan, Vunfu Wong; Alderman, John.

Unknown Host Publication. Vol. 4131 2006. p. 944-952.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - A Time Multiplexing Architecture for Inter-neuron Communications

AU - Tuffy, Fergal

AU - McDaid, Liam

AU - McGinnity, Martin

AU - Santos, Jose

AU - Kelly, Peter

AU - Kwan, Vunfu Wong

AU - Alderman, John

N1 - Reference text: 1. Roche, B., McGinnity, T.M., Maguire, L.P., McDaid, L.J.: Signalling Techniques and their Effect on Neural Network Implementation Sizes”, Information Sciences 132, pages 67-82, NH Elsevier, 2001 2. Murray, F., and Woodburn, R.: The Prospects for Analogue Neural VLSI, International Journal of Neural Systems, Vol. 8, No. 5 & 6, pages 559-579, Oct/Dec. 1997 3. Liu, S.C., Kramer, J., Indiveri, G., Delbruck, T., Burg, T., and Douglas, R.: Orientationselective VLSI Spiking Neurons, Neural Networks, Special Issue on Spiking Neurons in Neuroscience and Technology , Vol. 14, Issues 6-7, pages 629-643, July 2001 4. Diorio, C., Hsu, D., and Figueroa, M.: Adaptive CMOS: from biological inspiration to systems-on-a-chip, Proceedings of the IEEE, Vol. 90, Issue 3, pages 345 – 357, March 2002 5. Goldberg, D.H., Cauwenberghs, G., Andreou, A. G.: Probabilistic Synaptic Weighting in a Reconfigurable Network of VLSI Integrate-and-Fire Neurons, Neural Networks, Vol. 14, no. 6–7, pages 781–793, Sept 2001 6. Maass, W.: Computation with Spiking Neurons: the Handbook of Brain Theory and Neural Networks, MIT Press, 1998. 7. Noory, B., Groza, V.: A Reconfigurable Approach to Hardware Implementation of Neural Networks, IEEE CCECE 2003. Canadian Conference on Electrical and Computer Engineering, pages 1861 - 1864 Vol. 3, 4-7 May 2003 8. Chun, L., Shi, B., Chen, L.: Hardware Implementation of an Expandable On-chip Learning Neural Network with 8-Neuron and 64-Synapse, TENCON '02. Proceedings 2002 IEEE Region 10 Conference on Computers, Communications, Control and Power Engineering, Vol. 3, pages 1451 – 1454, 28-31 Oct. 2002 9. Miki, T., Editor: Brainware: Bio-Inspired Architectures and its Hardware Implementation, World Scientific Publishing Co. Ltd, 2001. 10. Johnston, S.P, Prasad, G., Maguire, L. P., McGinnity, T. M.: Comparative Investigation into Classical and Spiking Neuron Implementations on FPGAs, 15th International Conference on Artificial Neural Networks, ICANN 2005, Part 1: pages 269-274, 11-15 Sept. 2005 11. http://www.xilinx.com/ise/optional_prod/system_generator.htm 12. Tu, S.-W., Jou, J.-Y., Chang, Y.-W.: RLC Coupling-Aware Simulation for On-Chip Buses and their Encoding for Delay Reduction, 2005 ISCAS IEEE International Symposium on Circuits and Systems, 23-26 May 2005 Page(s):4134 - 4137 Vol. 4 13. Chicca, E., Badoni, D., Dante, V., D’Andreagiovanni, M., Salina, G., Carota, L., Fusi, S. and Del Giudice, P.: A VLSI Recurrent Network of Integrate and Fire Neurons Connected by Plastic Synapses with Long Term Memory”, IEEE Trans. on Neural Networks, Vol.14, No.5, Sept. 2003 14. Yamaoka, M., Osada, K., Ishibashi, K.: 0.4-V Logic-Library-Friendly SRAM Array Using Rectangular-Diffusion Cell and Delta-Boosted-Array Voltage Scheme, IEEE Journal of Solid-State Circuits, Volume 39, Issue 6, June 2004 Page(s):934 – 940 15. Naeemi, A., Meindl, J.D.: Monolayer Metallic Nanotube Interconnects: Promising Candidates or Short Local Interconnects, IEEE Electron Device Letters, Volume 26, Issue 8, Aug. 2005 Page(s):544 - 546

PY - 2006

Y1 - 2006

N2 - This paper presents a hardware implementation of a Time Multiplexing Architecture (TMA) that can interconnect arrays of neurons in an Artificial Neural Network (ANN) using a single metal wire. The approach exploits the relative slow operational speed of the biological system by using fast digital hardware to sequentially sample neurons in a layer and transmit the associated spikes to neurons in other layers. The motivation for this work is to develop minimal area inter-neuron communication hardware. An estimate of the density of on-chip neurons afforded by this approach is presented. The paper verifies the operation of the TMA and investigates pulse transmission errors as a function of the sampling rate. Simulations using the Xilinx System Generator (XSG) package demonstrate that the effect of these errors on the performance of an SNN, pre-trained to solve the XOR problem, is negligible if the sampling frequency is sufficiently high.

AB - This paper presents a hardware implementation of a Time Multiplexing Architecture (TMA) that can interconnect arrays of neurons in an Artificial Neural Network (ANN) using a single metal wire. The approach exploits the relative slow operational speed of the biological system by using fast digital hardware to sequentially sample neurons in a layer and transmit the associated spikes to neurons in other layers. The motivation for this work is to develop minimal area inter-neuron communication hardware. An estimate of the density of on-chip neurons afforded by this approach is presented. The paper verifies the operation of the TMA and investigates pulse transmission errors as a function of the sampling rate. Simulations using the Xilinx System Generator (XSG) package demonstrate that the effect of these errors on the performance of an SNN, pre-trained to solve the XOR problem, is negligible if the sampling frequency is sufficiently high.

U2 - 10.1007/11840817_98

DO - 10.1007/11840817_98

M3 - Conference contribution

SN - 978-3-540-38625-4

VL - 4131

SP - 944

EP - 952

BT - Unknown Host Publication

ER -

Tuffy F, McDaid L, McGinnity M, Santos J, Kelly P, Kwan VW et al. A Time Multiplexing Architecture for Inter-neuron Communications. In Unknown Host Publication. Vol. 4131. 2006. p. 944-952 https://doi.org/10.1007/11840817_98