Adaptive beamforming can play an important role in sensor array systems in countering directional interference. In highsample rate systems, such as radar and comms, the calculation of adaptive weights is a very computational task that requires highly parallel solutions. For systems where low power consumption and volume are important the only viable implementation is as an Application Specific Integrated Circuit (ASIC). However, the rapid advancement of Field Programmable GateArray (FPGA) technology is enabling highly credible re-programmable solutions. In this paper we present the implementation of a scalable linear array processor for weight calculation using QR decomposition. We employ floating-point arithmetic with mantissa size optimised to the target application to minimise component size, and implement them as relationally placed macros (RPMs) on Xilinx Virtex FPGAs to achieve predictable dense layout and high-speed operation. We present results that show that 20GFLOPS of sustained computation on a single XCV3200E-8 Virtex-E FPGA is possible. We also describe the parameterised implementation of the floating-point operators and QR-processor, and the design methodology that enables us to rapidly generate complex FPGA implementations using the industry standard hardware description language VHDL.
|Title of host publication||Unknown Host Publication|
|Place of Publication||Online|
|Number of pages||11|
|Publication status||Published (in print/issue) - 6 May 2003|
|Event||SPIE Advanced Signal Processing Algorithms, Architectures, and Implementations - San Diego, CA, USA|
Duration: 6 May 2003 → …
|Conference||SPIE Advanced Signal Processing Algorithms, Architectures, and Implementations|
|Period||6/05/03 → …|
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- array processor
- Smart Antenna
- Adaptive Beamforming