20-GFLOPS QR processor on a Xilinx Virtex-E FPGA

R Walke, R Smith, G Lightbody

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Citations (Scopus)

Abstract

Adaptive beamforming can play an important role in sensor array systems in countering directional interference. In highsample rate systems, such as radar and comms, the calculation of adaptive weights is a very computational task that requires highly parallel solutions. For systems where low power consumption and volume are important the only viable implementation is as an Application Specific Integrated Circuit (ASIC). However, the rapid advancement of Field Programmable GateArray (FPGA) technology is enabling highly credible re-programmable solutions. In this paper we present the implementation of a scalable linear array processor for weight calculation using QR decomposition. We employ floating-point arithmetic with mantissa size optimised to the target application to minimise component size, and implement them as relationally placed macros (RPMs) on Xilinx Virtex FPGAs to achieve predictable dense layout and high-speed operation. We present results that show that 20GFLOPS of sustained computation on a single XCV3200E-8 Virtex-E FPGA is possible. We also describe the parameterised implementation of the floating-point operators and QR-processor, and the design methodology that enables us to rapidly generate complex FPGA implementations using the industry standard hardware description language VHDL.
LanguageEnglish
Title of host publicationUnknown Host Publication
Place of PublicationOnline
PublisherSPIE
Pages300-310
Number of pages11
Volume4116
DOIs
Publication statusPublished - 6 May 2003
EventSPIE Advanced Signal Processing Algorithms, Architectures, and Implementations - San Diego, CA, USA
Duration: 6 May 2003 → …

Conference

ConferenceSPIE Advanced Signal Processing Algorithms, Architectures, and Implementations
Period6/05/03 → …

Fingerprint

Computer hardware description languages
Digital arithmetic
Sensor arrays
Application specific integrated circuits
Parallel processing systems
Beamforming
Macros
Field programmable gate arrays (FPGA)
Radar
Electric power utilization
Decomposition
Industry

Keywords

  • FPGA
  • DSP
  • QR
  • array processor
  • Radar
  • Smart Antenna
  • Adaptive Beamforming

Cite this

Walke, R., Smith, R., & Lightbody, G. (2003). 20-GFLOPS QR processor on a Xilinx Virtex-E FPGA. In Unknown Host Publication (Vol. 4116, pp. 300-310). Online: SPIE. https://doi.org/10.1117/12.406508
Walke, R ; Smith, R ; Lightbody, G. / 20-GFLOPS QR processor on a Xilinx Virtex-E FPGA. Unknown Host Publication. Vol. 4116 Online : SPIE, 2003. pp. 300-310
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title = "20-GFLOPS QR processor on a Xilinx Virtex-E FPGA",
abstract = "Adaptive beamforming can play an important role in sensor array systems in countering directional interference. In highsample rate systems, such as radar and comms, the calculation of adaptive weights is a very computational task that requires highly parallel solutions. For systems where low power consumption and volume are important the only viable implementation is as an Application Specific Integrated Circuit (ASIC). However, the rapid advancement of Field Programmable GateArray (FPGA) technology is enabling highly credible re-programmable solutions. In this paper we present the implementation of a scalable linear array processor for weight calculation using QR decomposition. We employ floating-point arithmetic with mantissa size optimised to the target application to minimise component size, and implement them as relationally placed macros (RPMs) on Xilinx Virtex FPGAs to achieve predictable dense layout and high-speed operation. We present results that show that 20GFLOPS of sustained computation on a single XCV3200E-8 Virtex-E FPGA is possible. We also describe the parameterised implementation of the floating-point operators and QR-processor, and the design methodology that enables us to rapidly generate complex FPGA implementations using the industry standard hardware description language VHDL.",
keywords = "FPGA, DSP, QR, array processor, Radar, Smart Antenna, Adaptive Beamforming",
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note = "Reference text: 1. A. Farina, Antenna-Based Signal Processing Techniques for Radar Systems, Artech House, 1991. 2. Xilinx Core Generator, http://support.xilinx.com/. 3. S. Haykin, Adaptive Filter Theory, 2nd Edition, Prentice Hall, ISBN 0-13-013236-5, 1991. 4. C. R. Ward, P. J. Hargrave, and J. G. McWhirter, “A Novel Algorithm and Architecture for Adaptive Digital Beamforming”, IEEE Trans. on Antennas and Propagation, Vol. AP-34, No. 3, pp. 338-346, 1986. 5. J . G. McWhirter, “Recursive least-squares minimization using a systolic array”, Proc. SPIE 431, Real-Time Signal Processing VI, pp. 105-112, 1983. 6. W. Givens, “Computation of Plane Unitary Rotations Transforming a General Matrix to Triangular Form”, J. Soc. Indust. Appl. Math., Vol. 6, No. 1, pp. 26-50, March 1958. 7. W. M. Gentleman and H. T. Kung, “Matrix triangularization by systolic arrays”, Proc. SPIE 298, Real-Time Signal Processing IV, pp. 19-26, 1981. 8. R. D{\"o}hler, “Squared Givens Rotations”, IMA J. of Numerical Analysis, Vol. 11, pp. 1-5, 1991. 9. J. Volder, “The CORDIC Trigonometric Computing Technique”, IRE Trans. Electron. Comput., Vol. EC-8, pp. 330-334, 1959. 10. R. Walke, R. W. M. Smith and G. Lightbody, “Architectures for Adaptive Weight Calculation on ASIC and FPGA”, Proc. 33rd Asilomar Conference on Signals, Systems and Computers, 1999. 11. S. Y. Kung, VLSI Array Processors, Prentice Hall, ISBN 0-13-942749-X, 1988. 12. G. M. Megson, An Introduction to Systolic Algorithm Design, Clarendon Press, ISBN 0-19-853813-8, 1992. 13. G. Lightbody, R. L. Walke, R. Woods, J. McCanny, “Linear QR Architecture for a Single Chip Adaptive Beamformer”, Journal of VLSI Signal Processing, Vol. 24, pp. 67-81, 2000. 14. Alliance Series 3.1i Software Documentation: Libraries Guide, http://support.xilinx.com/ 15. G. Lightbody, R. L. Walke, R. Woods, J. McCanny, “Novel Mapping of a Linear QR Architecture”, Proc. ICASSP, vol. IV, pp. 1933-6, 1999. 16. IEEE Standard for Binary Floating-Point Arithmetic, ANSI/IEEE Std 754-1985. 310 Proc.",
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Walke, R, Smith, R & Lightbody, G 2003, 20-GFLOPS QR processor on a Xilinx Virtex-E FPGA. in Unknown Host Publication. vol. 4116, SPIE, Online, pp. 300-310, SPIE Advanced Signal Processing Algorithms, Architectures, and Implementations, 6/05/03. https://doi.org/10.1117/12.406508

20-GFLOPS QR processor on a Xilinx Virtex-E FPGA. / Walke, R; Smith, R; Lightbody, G.

Unknown Host Publication. Vol. 4116 Online : SPIE, 2003. p. 300-310.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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N2 - Adaptive beamforming can play an important role in sensor array systems in countering directional interference. In highsample rate systems, such as radar and comms, the calculation of adaptive weights is a very computational task that requires highly parallel solutions. For systems where low power consumption and volume are important the only viable implementation is as an Application Specific Integrated Circuit (ASIC). However, the rapid advancement of Field Programmable GateArray (FPGA) technology is enabling highly credible re-programmable solutions. In this paper we present the implementation of a scalable linear array processor for weight calculation using QR decomposition. We employ floating-point arithmetic with mantissa size optimised to the target application to minimise component size, and implement them as relationally placed macros (RPMs) on Xilinx Virtex FPGAs to achieve predictable dense layout and high-speed operation. We present results that show that 20GFLOPS of sustained computation on a single XCV3200E-8 Virtex-E FPGA is possible. We also describe the parameterised implementation of the floating-point operators and QR-processor, and the design methodology that enables us to rapidly generate complex FPGA implementations using the industry standard hardware description language VHDL.

AB - Adaptive beamforming can play an important role in sensor array systems in countering directional interference. In highsample rate systems, such as radar and comms, the calculation of adaptive weights is a very computational task that requires highly parallel solutions. For systems where low power consumption and volume are important the only viable implementation is as an Application Specific Integrated Circuit (ASIC). However, the rapid advancement of Field Programmable GateArray (FPGA) technology is enabling highly credible re-programmable solutions. In this paper we present the implementation of a scalable linear array processor for weight calculation using QR decomposition. We employ floating-point arithmetic with mantissa size optimised to the target application to minimise component size, and implement them as relationally placed macros (RPMs) on Xilinx Virtex FPGAs to achieve predictable dense layout and high-speed operation. We present results that show that 20GFLOPS of sustained computation on a single XCV3200E-8 Virtex-E FPGA is possible. We also describe the parameterised implementation of the floating-point operators and QR-processor, and the design methodology that enables us to rapidly generate complex FPGA implementations using the industry standard hardware description language VHDL.

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KW - QR

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Walke R, Smith R, Lightbody G. 20-GFLOPS QR processor on a Xilinx Virtex-E FPGA. In Unknown Host Publication. Vol. 4116. Online: SPIE. 2003. p. 300-310 https://doi.org/10.1117/12.406508