Research output per year
Research output per year
Personal profile
Biography
Dr. Japa Aditya is a Lecturer in School of Computing, Engineering and Intelligent Systems, Ulster University, Derry, U.K.
Dr. Japa received a Ph.D. degree in ECE, from Dr. SPM IIIT Naya Raipur, Chhattisgarh, India in 2021, with a focus on Emerging Technologies for Hardware security. After his Ph.D., he worked as a Research Fellow with the Centre for Secure Information Technologies, EEECS Department, Queen’s University, Belfast, U.K. His research mainly focuses on Hardware and System Security. He worked on emerging/beyond CMOS-based security strategies, PUF, TRNG, power side-channel analysis, and countermeasures. His current research interests include the design of PUFs, secure neural network accelerators (NNAs), security in/for approximate computing, and compute-in-memory based security stragies.
Expertise related to UN Sustainable Development Goals
In 2015, UN member states agreed to 17 global Sustainable Development Goals (SDGs) to end poverty, protect the planet and ensure prosperity for all. This person’s work contributes towards the following SDG(s):
Education/Academic qualification
PhD, Tunnel FET based Energy Efficient Circuit Design with Enhanced Hardware security
Award Date: 27 Nov 2021
Keywords
- TK Electrical engineering. Electronics Nuclear engineering
- Hardware Security
- Security in/for Approximate Computing
- Side-Channel Analysis
- Security of Neural Network Accelerators
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Collaborations and top research areas from the last five years
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Design Insights and Performance Analysis of VGSOT-MTJ for Energy-Efficient Logic and Memory
Kartheek, T., Kommu, S., Japa, A. & Gupta, D., 14 Jul 2025, (Published online) VLSI SATA 2025 - 5th IEEE International Conference on VLSI Systems, Architecture, Technology and Applications. IEEE, p. 1-6 6 p. (VLSI SATA 2025 - 5th IEEE International Conference on VLSI Systems, Architecture, Technology and Applications).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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Ferroelectric FET LUT Based Energy Efficient and Secure Logic Locking Resilient to SAT Attacks
Rao, K. T., Rao, P. K., Tanniru, R., Kommineni, P., Japa, A. & Vaddi, R., 14 Jul 2025, (Published online) VLSI SATA 2025 - 5th IEEE International Conference on VLSI Systems, Architecture, Technology and Applications. IEEE, p. 1-6 6 p. (VLSI SATA 2025 - 5th IEEE International Conference on VLSI Systems, Architecture, Technology and Applications).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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FeSATLock: An Energy Efficient and SAT Attack Resilient Logic Locking Design With FeFET LUT Architecture for Enhanced Hardware Security
Rao Kadiyam, T., Birudu, V., Japa, A., Sibai, F. N., Gonuguntla, V. & Vaddi, R., 21 Aug 2025, In: IEEE Access. 13, p. 144271-144286 16 p.Research output: Contribution to journal › Article › peer-review
Open AccessFile1 Citation (Scopus)7 Downloads (Pure) -
Security of Approximate Neural Networks against Power Side-channel Attacks
Japa, A., Miskelly, J., O’Neill, M. & Gu, C., 15 Sept 2025, (Published online) 2025 62nd ACM/IEEE Design Automation Conference (DAC). IEEE, p. 1-7 7 p.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review